Ventana has launched its Veyron V2 RISC-V processor design targeting data center operators and hyperscalers in an effort to help them design their servers with high precision and at a much faster scale.
Shortly after launching the Veyron V1 chiplets earlier this year, the company is rolling out a successor that can offer an IO hub and accelerators that work with the UCI-Express chiplet connectivity standard to provide 192 cores per socket.
In a conceptual example, six 32-core V2 chiplets were connected to the IO hub via UCI-Express and extended with domain-specific acceleration. The IO hub can also connect to memory and components via DDR5 and PCIe 5.0 controllers. However, the company says organizations can swap DDR5 controllers for HBM3 controllers if they wish Next platform.
Hyperscalers pay attention to Ventana
The reason Ventana brought its next generation to market after Veyron V1 was only launched earlier this year is the fact that this version used the Bunch of Wires (BoW) standard for interconnecting chiplets – the best yet was available at the time.
But Intel then launched the UCI-Express standard in March last year, which proved to be the superior option for connecting chiplets, and Ventana wasted no time in integrating this technology into the next version of its chip technology.
One of the most promising aspects of this part is benchmarking, with the company’s figures showing that the 192-core Veyron 2 RISC-V CPU beats several competitors quite easily in terms of throughput.
These include the 64-core Arm Neoverse V2, 56-core Intel
The Ventana Veyron V2 processor boasted 23% more integers than AMD’s Bergamo CPU, one of the fastest processors available, making it a highly competitive option for businesses.
The base model of the Veyron V2 design comes with four chiplets for 128 cores and eight DDR5 RAM channels, and will go into production in the third quarter of next year. This is because production is dependent on the UCI-Express 1.1 PHY standard becoming available.